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datasheet low phase noise,1-to-4, 3.3v, 2.5v lvpecl output fanout buffer IDT8SLVP1104I idt8slvp1104anlgi revision a february 25, 2014 1 ?2014 integrated device technology, inc. general description the IDT8SLVP1104I is a high-per formance differential lvpecl fanout buffer. the device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. the IDT8SLVP1104I is characterized to operate from a 3.3v or 2.5v power supply. guaranteed output-to-output and part-to-part skew characteristics make the IDT8SLVP1104I ideal for those clock distribution applications demandin g well-defined performance and repeatability.four low skew outputs are available. the integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. the device is optimized for low power consumption and low additive phase noise. features ? four low skew, low additive jitter lvpecl differential output pairs ? differential lvpecl input pair can accept the following differential input levels: lvds, lvpecl, cml ? differential pclkx pairs can also accept single-ended lvcmos levels. see the applications sect ion writing the differential input levels to accept single-ended levels (figures 1 and 2) ? maximum input clock frequency: 2ghz ? lvcmos interface levels for t he control input (input select) ? output skew: 5ps (typical) ? propagation delay: 320ps (maximum) ? low additive phase jitter, rms; f ref = 156.25mhz, v pp = 1v, 12khz - 20mhz: 40fs (maximum) ? maximum device current consumption (i ee ): 60ma (maximum) ? full 3.3v or 2.5v supply voltage ? lead-free (rohs 6) packaging ? -40c to 85c ambient operating temperature block diagram pin assignment IDT8SLVP1104I 16 lead vfqfn 3.0mm x 3.0mm x 0.925mm package body 1.7mm x 1.7mm epad size nl package top view f ref pclk npclk v ref v cc q0 nq0 q1 nq1 q2 nq2 q3 nq3 pulldown pullup/pulldown voltage reference 1 2 3 4 12 11 10 9 13 14 15 16 8 7 6 5 q2 nq2 q3 nq3 v ref npclk pclk v cc v ee nc nc nc q1 nq0 q0 nq1
idt8slvp1104anlgi revision a february 25, 2014 2 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer pin descriptions and characteristics table 1. pin descriptions note: pulldown and pullup refers to an internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1v ee power negative supply pin. 2 nc unused do not connect. 3 nc unused do not connect. 4 nc unused do not connect. 5v cc power power supply pin. 6 pclk input pulldown non-inverting differentia l lvpecl clock/data input. 7npclkinput pullup/ pulldown inverting differential lvpecl clock/data input. v cc /2 default when left floating. 8v ref output bias voltage reference for the pclk inputs. 9, 10 q0, nq0 output differential ou tput pair 0. lvpec l interface levels. 11, 12 q1, nq1 output differential ou tput pair 1. lvpec l interface levels. 13, 14 q2, nq2 output differential ou tput pair 2. lvpec l interface levels. 15, 16 q3, nq3 output differential ou tput pair 3. lvpec l interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 2 pf r pulldown input pulldown resistor 51 k ? r pullup input pullup resistor 51 k ?
idt8slvp1104anlgi revision a february 25, 2014 3 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operati on of product at these conditions or an y conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating condit ions for extended periods may affect product reliability. note 1: according to jedec/jesd 22-a114/22-c101. dc electrical characteristics table 3a. power supply dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = -40c to 85c table 3b. power supply dc characteristics, v cc = 2.5v 5%, v ee = 0v, t a = -40c to 85c table 3c. lvpecl dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = -40c to 85c note 1: outputs terminated with 50 ? to v cc ? 2v. item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o (lvpecl) continuous current surge current 50ma 100ma input sink/source, i ref 2ma maximum junction temperature, t j,max 125c storage temperature, t stg -65 ? c to 150 ? c esd - human body model, note 1 2000v esd - charged device model, note 1 1500v symbol parameter test conditions minimum typical maximum units v cc power supply voltage 3.135 3.3v 3.465 v i ee power supply current 53 60 ma i cc power supply current q0 to q3 terminated 50 ? to v cc ? 2v 170 204 ma symbol parameter test conditions minimum typical maximum units v cc power supply voltage 2.375 2.5v 2.625 v i ee power supply current 49 55 ma i cc power supply current q0 to q3 terminated 50 ? to v cc ? 2v 170 199 ma symbol parameter test conditio ns minimum typical maximum units i ih input high current pclk, npclk v cc = v in = 3.465v 150 a i il input low current pclk v cc = 3.465v, v in = 0v -10 a npclk v cc = 3.465v, v in = 0v -150 a v ref reference voltage for input bias i ref = 1ma v cc ? 1.6 v cc ? 1.3 v cc ? 1.1 v v oh output high voltage; note 1 v cc ? 1.1 v cc ? 0.9 v cc ? 0.7 v v ol output low voltage; note 1 v cc ? 2.0 v cc ? 1.65 v cc ? 1.5 v
idt8slvp1104anlgi revision a february 25, 2014 4 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer table 3d. lvpecl dc characteristics, v cc = 2.5v 5%, v ee = 0v, ta = -40c to 85c note 1: outputs terminated with 50 ? to v cc ? 2v. symbol parameter test conditio ns minimum typical maximum units i ih input high current pclk, npclk v cc = v in = 2.625v 150 a i il input low current pclk v cc = 2.625v, v in = 0v -10 a npclk v cc = 2.625v, v in = 0v -150 a v ref reference voltage for input bias i ref = 1ma v cc ? 1.6 v cc ? 1.3 v cc ? 1.1 v v oh output high voltage; note 1 v cc ? 1.1 v cc ? 0.9 v cc ? 0.7 v v ol output low voltage; note 1 v cc ? 2.0 v cc ? 1.6 v cc ? 1.5 v
idt8slvp1104anlgi revision a february 25, 2014 5 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer ac electrical characteristics table 4. ac electrical characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: measured from the differential input crossing point to the differential output crossing point. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the differential crosspoints. note 3: this parameter is defined in accordance with jedec standard 65. notes continued on next page. symbol parameter test conditio ns minimum typical maximum units f ref input frequency pclk, npclk 2ghz ? v/ ? t input edge rate pclk, npclk 1.5 v/ns t pd propagation delay; note 1 pck, npclk to any q[0:3], nq[0:3] for v pp = 0.1v or 0.3v 120 200 320 ps t sk(o) output skew; note 2, 3 525ps t sk(p) pulse skew f ref = 100mhz 5 20 ps t sk(pp) part-to-part skew; note 3, 4 100 200 ps t jit buffer additive phase jitter, rms; refer to additive phase jitter section f ref = 122.88mhz sine wave, v pp = 1v, integration range: 1khz ? 40mhz 170 fs f ref = 122.88mhz sine wave, v pp = 1v, integration range: 10khz ? 20mhz 114 fs f ref = 122.88mhz sine wave, v pp = 1v, integration range: 12khz ? 20mhz 114 fs f ref = 156.25mhz square wave, v pp = 1v, integration range: 1khz ? 40mhz 42 51 fs f ref = 156.25mhz square wave, v pp = 1v, integration range: 10khz ? 20mhz 32 40 fs f ref = 156.25mhz square wave, v pp = 1v, integration range: 12khz ? 20mhz 32 40 fs f ref = 156.25mhz square wave, v pp = 0.5v, integration range: 1khz ? 40mhz 51 71 fs f ref = 156.25mhz square wave, v pp = 0.5v, integration range: 10khz ? 20mhz 38 52 fs f ref = 156.25mhz square wave, v pp = 0.5v, integration range: 12khz ? 20mhz 38 52 fs t r / t f output rise/ fall time 20% to 80% 35 180 ps v pp peak-to-peak input voltage; note 5, 6 f ref < 1.5 ghz 0.1 1.5 v f ref > 1.5 ghz 0.2 1.5 v v cmr common mode input voltage; note 5, 6, 7 1.0 v cc ? 0.6 v v o (pp) output voltage swing, peak-to-peak v cc = 3.3v, f ref ?? 2ghz 0.45 0.75 1.0 v v cc = 2.5v, f ref ?? 2ghz 0.4 0.65 1.0 v v diff_out differential output voltage swing, peak-to-peak v cc = 3.3v, f ref ?? 2ghz 0.9 1.5 2.0 v v cc = 2.5v, f ref ?? 2ghz 0.8 1.3 2.0 v
idt8slvp1104anlgi revision a february 25, 2014 6 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer note 4: defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same tempera ture and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross po ints. note 5: for single-ended lvcmos input applications, refer to the applications section writing the differential in put levels to accept single-ended levels (figures 1 and 2). note 6: v il should not be less than -0.3v. note 7: common mode input voltage is defined as the crosspoint.
idt8slvp1104anlgi revision a february 25, 2014 7 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundament al frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specificat ions, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device me ets the noise floor of what is shown, but can actually be lowe r. the phase noise is dependent on the input source and measurement equipment. measured using a wenzel 156.25mhz oscillator as the input source. offset from carr ier frequency (hz) ssb phase noise dbc/hz f ref = 156.25mhz, v pp = 1v, integration range 12khz ? 20mhz: 40fs (maximum)
idt8slvp1104anlgi revision a february 25, 2014 8 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer parameter measureme nt information 3.3v lvpecl output load test circuit differential input level part-to-part skew 2.5v lvpecl output load test circuit output skew pulse skew scope qx nqx v ee v cc 2v -1.3v0.165v v cc v ee npclk pclk t sk(pp) part 1 part 2 nqx qx nqy qy scope qx nqx v ee v cc 2v -0.5v0.125v nqx qx nqy qy t plh t phl tsk(p) = |t phl - t plh | npclk pclk nqy qy
idt8slvp1104anlgi revision a february 25, 2014 9 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer parameter measurement in formation, continued propagation delay output rise/fall time t pd npclk pclk pclk q[0:3] nq[0:3] q[0:3]
idt8slvp1104anlgi revision a february 25, 2014 10 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer applications information wiring the differential input to accept single-ended levels the IDT8SLVP1104I in puts can be interfaced to lvpecl, lvds, cml or lvcmos drivers. figure 1a illustrates how to dc couple a single lvcmos input to the idt8sl vp1104i. the value of the series resistance rs is calculated as the difference between the transmission line impedance and the driver output impedance. this resistor should be placed close to the lvcmos driver. to avoid cross-coupling of single-ended lvcmos signals, apply the lvcmos signals to no more than one pclk input. a practical method to implement vth is shown in figure 1b below. the reference voltage vth = v1 = v cc /2, is generated by the bias resistors r1 and r2. the bypass capaci tor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v1 in the center of the input voltage s wing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v1 at 1.25v. the va lues below apply when both the single-ended swing and v cc are at the same voltage. figure 1a. dc-coupling a singl e lvcmos input to the IDT8SLVP1104I when using single-ended signaling, the noise rejection benefits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced, particularly if both input references are lvcmos to minimize cross talk. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. figure 1b shows a way to attenuate the pclk input level by a factor of two as well as matching the transmission line between the lvcmos driver and the IDT8SLVP1104I at both the source and the load. this configuration require s that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. r3 and r4 in parallel should equal the transmission line impedance; for most 50 ? applications, r3 and r4 will be 100 ? . the values of the resi stors can be increased to reduce the loading for slower and weaker lvcmos driver. though some of the recommended components of figure 1b might not be used, the pads should be placed in the layout so that they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1b. alternative dc coupling a singl e lvcmos input to the IDT8SLVP1104I r s lvcmos v th = v ih + v il 2 v th v ih v il rec eiv er + - r4 10 0 r3 10 0 rs zo = 50 ohm ro driv er vcc vcc r2 1k r1 1k c1 0.1uf ro + rs = zo v1 vc c vc c
idt8slvp1104anlgi revision a february 25, 2014 11 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer 3.3v lvpecl clock input interface the pclk /npclk accepts l vpecl, lvds, cml and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 2a to 2e show interface examples for the pclk/ npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 2a. pclk/npclk input driven by a cml driver figure 2c. pclk/npclk input driven by a 3.3v lvpecl driver figure 2e. pclk/npclk input driven by a 3.3v lvds driver figure 2b. pclk/npclk input driven by a built-in pullup cml driver figure 2d. pclk/npclk input driven by a 3.3v lvpecl driver with ac couple p c l k np c l k lvpecl in p u t c m l 3 . 3v 3 . 3v 3 . 3 v r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 zo = 50 pclk npclk 3.3v 3.3v lvpecl lvpecl input 3 . 3v r1 1 00 ? ? ? pclk npclk 3.3v lvpecl input 3.3v zo = 50 zo = 50 r1 100 cml built-in pullup
idt8slvp1104anlgi revision a february 25, 2014 12 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer 2.5v lvpecl clock input interface the pclk /npclk accepts l vpecl, lvds, cml and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 3a to 3e show interface examples for the pclk/ npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 3a. pclk/npclk input driven by a cml driver figure 3c. pclk/npclk input driven by a 2.5v lvpecl driver figure 3e. pclk/npclk input driven by a 2.5v lvds driver figure 3b. pclk/npclk input driven by a built-in pullup cml driver figure 3d. pclk/npclk input driven by a 2.5v lvpecl driver with ac couple p c l k np c l k lvpecl in p u t c m l 2. 5v 2. 5v 2. 5 v 2. 5v p c l k np c l k 2. 5v 2. 5v lvpe cl lvpe c l in p u t p c l k np c l k p c l k np c l k 2. 5v lvpe c l in p u t 2. 5v cml built-in pullu p
idt8slvp1104anlgi revision a february 25, 2014 13 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer recommendations for un used output pins outputs: lvpecl outputs all unused lvpecl outputs can be le ft floating. we recommend that there is no trace attached. both si des of the differential output pair should either be left floating or terminated. vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 4. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
idt8slvp1104anlgi revision a february 25, 2014 14 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are a lo w impedance follower output that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current pa th to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 5a and 5b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 5a. 3.3v lvpecl output termination figure 5b. 3.3v lvpecl output termination r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v + _
idt8slvp1104anlgi revision a february 25, 2014 15 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer termination for 2.5v lvpecl outputs figure 6a and figure 6b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc ? 2v. for v cc = 2.5v, the v cc ? 2v is very close to ground level. the r3 in figure 6b can be eliminated and the termination is shown in figure 6c. figure 6a. 2.5v lvpecl driver termination example figure 6c. 2.5v lvpecl driver termination example figure 6b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 50 r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r1 50 r2 50 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r1 50 r2 50 r3 18 + ?
idt8slvp1104anlgi revision a february 25, 2014 16 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer power considerations this section provides information on power dissipati on and junction temperature for the IDT8SLVP1104I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the IDT8SLVP1104I is the sum of the core power plus the power dissipated due to loading. the following is the power dissipation for v cc = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated due to loading. the maximum current at 85 is as follows: i ee_max = 60ma ? power (core) max = v cc_max * i ee_max = 3.465v * 60ma = 207.9mw ? power (outputs) max = 33.2mw/loaded output pair if all outputs are loaded, the total power is 4 * 33.2mw = 132.8mw total power_ max (3.465v, with all outputs swit ching) = 207.9mw + 132.8mw = 340.7mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 74.7c/w per table 5 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.341w * 74.7c/w = 110.5c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 5. thermal resistance ? ja for 16-lead vfqfn, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 74.7c/w 65.3c/w 58.5c/w
idt8slvp1104anlgi revision a february 25, 2014 17 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pair. lvpecl output driver circuit and termination are shown in figure 7. figure 7. lvpecl driver circuit and termination to calculate power dissipation due to loading, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. these are typical calculations. ? for logic high, v out = v oh_max = v cc_max ? 0.7v (v cc_max ? v oh_max ) = 0.7v ? for logic low, v out = v ol_max = v cc_max ? 1.5v (v cc_max ? v ol_max ) = 1.5v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = [(2v ? 0.7v)/50 ? ] * 0.7v = 18.2mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l ] * (v cc_max ? v ol_max ) = [(2v ? 1.5v)/50 ? ] * 1.5v = 15mw total power dissipation per output pair = pd_h + pd_l = 33.2mw v out v cc v cc - 2v q1 rl
idt8slvp1104anlgi revision a february 25, 2014 18 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer reliability information table 6. ? ja vs. air flow table for a 16-lead vfqfn transistor count the transistor count for the IDT8SLVP1104I is: 258 ? ja at 0 air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 74.7c/w 65.3c/w 58.5c/w
idt8slvp1104anlgi revision a february 25, 2014 19 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer 16-lead vfqfn package out line and package dimensions
idt8slvp1104anlgi revision a february 25, 2014 20 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer ordering information table 7. ordering information part/order number marking package shipping packaging temperature 8slvp1104anlgi 104ai ?lead-free? 16-lead vfqfn tube -40 ? c to 85 ? c 8slvp1104anlgi8 104ai ?lead-free? 16-lead vfqfn tape & reel -40 ? c to 85 ? c
idt8slvp1104anlgi revision a february 25, 2014 21 ?2014 integrated device technology, inc. IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer revision history sheet rev table page description of change date a t7 20 ordering info: changed tray to tube. 2/25/2014
IDT8SLVP1104I data sheet low phase noise, 1:4, 3.3v, 2.5v lvpecl output fanout buffer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmenta l conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an id t product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2014. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support sales netcom@idt.com +480-763-2056 we?ve got your timing solution

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